1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device including a clock generation circuit that generates an internal clock in synchronization with a reference clock.
2. Description of the Background Art
Personal computers and work stations include a memory to store data. Among the memories, a DRAM (Dynamic Random Access Memory) that can read out and write data in large capacity is known to be used as the main memory for personal computers and work stations. Recently, a DDR SDRAM (Double Data Rate Synchronous Random Access Memory) is beginning to be used as the main memory for a work station.
This DDR SDRAM operates in synchronization with an externally applied clock signal. The DDR SDRAM includes a DLL (Delay Locked Loop) circuit to generate an internal clock signal in synchronization with an externally applied clock signal. The circuit in the DDR SDRAM operates in synchronization with this internal clock signal.
FIG. 16 shows a conventional DLL circuit disclosed in, for example, Japanese Patent Laying-Open No.11-120769. When an internal clock signal CLK1 in synchronization with a clock pulse ECLK is to be generated using this conventional DLL circuit, there is a possibility that the pulse will disappear during the passage through a delay line if the pulse width of clock pulse ECLK is small.